Random defects occurring during the manufacturing of an integrated circuit with embedded memory blocks that can render certain non-redundant elements of an integrated circuit memory device, such as a memory column, defective. For example, particle contamination during the manufacturing process may cause broken or shorted out columns and bit defects.
Redundant elements in an integrated circuit memory device, such as redundant columns, are used to compensate for these random defects. Initial testing of an integrated circuit memory occurs after the manufacturing process. During the initial manufacturing testing of an integrated circuit memory device, defective elements are replaced by non-defective elements referred to as redundant elements. Thus, redundant components, such as redundant columns and redundant rows, may be used in a scheme to replace defective non-redundant components, discovered during initial testing of the integrated circuit memory device. Typically, once a test of a memory occurs a repair signature is generated. A repair signature is typically a binary coded sequence that identifies the defective components detected and the redundant components allocated to replace those components. The use of redundant elements and a repair signature is important in increasing the overall yield of manufacturing integrated circuits with memory devices in a single chip.
FIG. 1 illustrates a block diagram of a previous technology to generate a repair signature for an embedded memory possessing a redundancy structure used in a system on a chip (SoC). SoC 102 integrates on-chip memory 104 with processors and other similar components, all on the same chip, to decrease cost and increase performance. Redundancy techniques include adding extra memory rows and memory columns that can be substituted for defective components within the memory. The prior external test solution creates a hard repair signature under one set of conditions. The single set of conditions is typically standard operating temperature and voltage.
Four equipment insertions may be required when testing SoC memory 104. First, the external memory tester 108 tests the memory to find defective components on the SoC 102 die. The external memory tester 108 imports the failure results in order to perform redundancy analysis and allocation. The external memory tester 108 sends the repair signature, or in other words the information on how to allocate the repair elements for any defects, to the laser repair equipment 110. Second, the laser repair equipment 110 blows the fuses on the SoC 102 wafer that enable the redundant rows and memory columns to be substituted for the defective memory cells. Third, the memory tester 108 re-tests memory on the SoC 102 to ensure that the repairs were made properly. Last, the logic tester 112 analyzes the remaining non-memory components of the SoC 102.
The typical external test solution limits the detection of defective components to defects occurring during the manufacturing process and at standard environmental conditions and not defects that occur after the SoC is in operation or atypical environmental conditions such as high and low temperatures, high and low levels of operating voltages, high and low frequency conditions, etc. Further, the typical external solution may run a first test algorithm to determine defects in the memory or a second test algorithm to determine the defects in the memory. Test algorithms are typically rated to detect a given percentage of the actual defects that exist in a memory, such as 95% effective or 99% effective. The manufacturer may then choose to apply the results of the first test algorithm or the second test algorithm to repair a memory. However, no way exists to compare the results of the first test algorithm and the second test algorithm to repair all the defects detected by either the first test algorithm and the second test algorithm. Also, memory tester 108 may not be able to test the memories at the speed of the chip. Thus, potential defects that only occur when the memory is operating at speed may not be detected.